Computers and other electronic equipment are becoming more powerful and can perform a wider range of tasks. To prevent growth in the sizes of the computers and other electronic equipment and operate them at higher speeds, the electronic circuits use miniature electronic components in high density packing arrangements. One such miniature electronic component, a solid state capacitor, is a tiny rectangular “chip” that is smaller than a grain of rice. FIG. 1 shows a capacitor chip 10 that has a solid enclosed body 12 of square or rectangular cross section and made of ceramic or other dielectric material. Capacitor chip 10 contains within body 12 multiple spaced-apart metal plates (not shown). One terminal end of each of alternate metal plates is connected to the exterior of body 12 and is adapted by a metallizing process to form a pair of spaced-apart mutually opposed electronic contact surfaces or ends 14. One or more of the contact surfaces 14 of chip capacitor 10 are striped with a solderable paste that is dried and then fired to produce surfaces that later can be soldered directly onto a circuit board. U.S. Pat. No. 5,226,382 describes a machine for placing a stripe or trace of solderable paste on surfaces of a chip and drying the paste so that the paste can later be fired. This machine uses a metal carrier belt or tape in which slotted rubber masks are formed. The slots in the masks receive chips in position for processing, such as covering opposed ends of the chips with solderable paste.
A relatively new electronic circuit chip is composed of multiple circuit components fit into a single array chip that is simultaneously solderable to one of a number of different electronic circuits. This device is called an Integrated Passive Component (IPC) or array chip because it comprises a plurality or array of circuit components, such as four or five separate capacitors stacked together in a single chip.
FIG. 2A shows a typical IPC or array chip 20 with its side wall surfaces covered with stripes 22 of solderable paste. Array chip 20 has overall dimensions such as 3.2 mm (0.125 in) long and 1.5 mm (0.060 in) wide top and bottom surfaces 24, 1.5 mm (0.060 in) wide and 1.0 mm (0.040 in) high opposed end surfaces 26, and 1.0 mm (0.040 in) high and 3.2 mm (0.125 in) long opposed side surfaces 28. FIG. 2B shows that installing array chip 20 into an electronic circuit entails placing separate solderable paste stripes 22 along opposite wall surfaces, such as side surfaces 28 (as shown) or end surfaces 26 (not shown), and soldering paste stripes 22 to copper traces 30 formed on a circuit board 32. The width of each stripe 22 is typically set at 0.38±0.18 mm (0.015±0.007 in), with a 0.3±0.18 mm (0.012±0.007 in) turn-down edge at the end of each stripe along the adjacent wall as shown on top and bottom surfaces 24 in FIG. 2A. As with other chip components, after the paste is applied, it is subjected to a heat-drying cycle to set the paste and thereafter to a firing cycle to fuse the paste on array chip 20.
The small size of a chip and the small differences between its width and height dimensions raise the importance of handling the chip and its insertion into the mask of a carrier belt or tape. The multiple stripes are placed on only the appropriate circuit board surfaces, and their placement is accomplished with extreme accuracy. Splashing of the paste onto other surfaces of the chip would provide a site for a short circuit and thereby significantly degrade electronic equipment function. Accordingly, a feed device places the chip onto the carrier tape in a correct position and location, and the chip is handled correctly so that the appropriate surface is exposed in proper orientation to receive the stripes of paste within a specified accuracy.
There are two principal types of miniature component carriers that transport the components and present them for processing. A first type of carrier is an endless belt or tape that is typically used to carry single component chips, such as capacitor chips 10, which are larger than array chips. The endless tape is formed with a plurality of transversely oriented elongated apertures arranged centrally between and uniformly spaced apart along the marginal edges of the tape. Each of the apertures is adapted to receive in coplanar fixed registration a thin, resilient mask having at least one orifice and preferably a series of orifices of sizes and shapes to compliantly receive the chips in specific orientation so that their end surfaces intended for termination extend outwardly from the masks.
A second type of carrier is an endless belt that is typically used to carry array chips such as array chips 20. The belt has a core typically made of stainless steel with multiple apertures spaced apart along the belt length. A thin elastomeric material, such as silicone rubber, is molded over the stainless steel core to form a resilient mask. A slot is formed during the molding process in the resilient mask at locations where the over-molded elastomeric material covers the apertures.
Silicone rubber is difficult to aver mold onto the belt because silicone rubber flows well through small cracks in the mold. For this reason, slot openings with precise dimensions are difficult to form. The array chip component is held in the slot under compression by an interference fit. A 0.05 mm (0.002 in) desired interference fit nominally requires a ±0.025 mm (±0.001 in) slot opening tolerance range. For example, a 5.1 mm (0.20 in) thick array chip component typically requires a 0.43-0.48 mm (0.017-0.019 in) slot opening. A less than a −0.025 mm (−0.001 in) slot opening width tolerance results in a slot that is too tight, causing the silicone rubber nubs of the slot opening to deflect (rather than compress) and thereby cant the array chip component held in the slot. A slot opening width of greater than 0.025 mm (0.001 in) lets the component fall out of the belt.
The use of precision moldings typically provides a 25 percent initial yield in dimensionally accurate slot openings, and the belt needs to be reworked to increase the yield to a 65-80 percent nominal yield benchmark. Yield represents the number of chip components that remain in their associated slot openings during processing. Variations in the thickness dimension of the chip components also contribute to the relatively low yield achieved with the 0.05 mm (0.002 in) interference fit.
What is needed, therefore, is a method of accurately forming with high initial yields component slots in a miniature component carrier belt to precise dimensions and close tolerances.